multiplier

module unsigned_mul
#(parameter width=8)(input [width-1:0] dataa
                                    input [width-1:0] datab,
                                 output [2*width-1:0] dataout
                                );
assign dataout=dataa*datab;
endmodule
/* -----------------------------------------------------------------------------------------*/
module signed_mul
#(parameter width=8)(input signed [width-1:0] dataa,
                                    input signed [width-1:0] datab,
                                output [2*width-1:0] dataout
                               );
assign dataout=dataa*datab;
endmodule
/* -----------------------------------------------------------------------------------------*/
module unsigned_mul
#(parameter width=8)(input clk,
                                    input [width-1:0] dataa,
                                    input [width-1:0] datab,
                output [2*width-1:0] dataout
                               );
reg [width-1:0] dataa_reg;
reg [width-1:0] datab_reg;
wire [2*width-1:0] mul_out;
assign mul_out=dataa_reg*datab_reg;
always@(posedge clk)
begin
dataa_reg<=dataa;
datab_reg<=datab;
dataout<=mul_out;
end
endmodule
/* -----------------------------------------------------------------------------------------*/
module signed_mul
#(parameter width=8)(input clk,
                                    input signed [width-1:0] dataa,
                                    input signed [width-1:0] datab,
                                 output reg signed [2*width-1:0] dataout
                                );
reg signed [width-1:0] dataa_reg;
reg signed [width-1:0] datab_reg;
wire signed [2*width-1:0] mul_out;
assign mul_out=dataa_reg*datab_reg;
always@(posedge clk)
begin
dataa_reg<=dataa;
datab_reg<=datab;
dataout<=mul_out;
end
endmodule
/* -----------------------------------------------------------------------------------------*/
module complex_mul
#(parameter width=8)(input clk,ena,
                                    input signed [width-1:0] dataa_real,dataa_imag,
                                    input signed [width-1:0] datab_real,datab_imag,
                                output reg signed [2*width-1:0] dataout_real,dataout_imag
                                );

always@(posedge clk)
if(ena==1)
begin
dataout_real<=dataa_real*datab_real-dataa_imag*datab_imag;
dataout_imag<=dataa_real*datab_imag+datab_real*dataa_imag;
end
end
endmodule